The present invention relates to electronic circuits, and more particularly, to techniques for decision feedback equalization that reduce variations in the tap weight.
A high-speed serial interface (“HSSI”) may be used to communicate between devices in a system. Typically, a transmitter in such a system transmits a signal to a receiver. The medium that conveys the signal from the transmitter to the receiver usually imposes losses on the signal being transmitted. To maintain accurate, high-speed data transmission, it is necessary for the circuitry to compensate for these losses.
Equalization circuitry is typically among the first circuitry that the incoming signal encounters when it reaches the receiver. Equalization circuitry is designed to respond strongly and rapidly to any transition detected in the received signal. This strong and rapid response restores the original steepness to these transitions, thereby making it possible for further circuitry of the receiver to correctly interpret the signal, even at the very high data rate of that signal.
Decision feedback equalization is a type of equalization that may be performed to compensate for distortion caused by the spreading and overlapping of bits in a data signal (i.e., inter-symbol interference). FIG. 1 illustrates an example of a prior art system that includes a decision feedback equalizer (DFE) 102. In the system of FIG. 1, a receiver circuit 101 receives a differential input voltage signal VIP/VIN at its input terminals. Typically, the differential input voltage signal VIP/VIN is transmitted to receiver 101 through external transmission lines. Receiver 101 transmits the data bits in the differential input voltage signal to inputs of decision feedback equalizer (DFE) circuit 102 and to inputs of clock data recovery (CDR) circuit 103 as a differential output voltage signal VOP/VON.
DFE circuit 102 includes a decision circuit 104, a current mode logic (CML) multiplexer (MUX) buffer circuit 105, a tap driver circuit 106, and a current source 107. Decision circuit 104 samples differential output voltage signal VOP/VON to generate even and odd digital sampled bits DE and DO in alternating unit intervals in response to clock signal CLK. Each unit interval corresponds to one bit period in differential voltage signal VOP/VON. Two unit intervals equal one clock period of clock signal CLK.
CML multiplexer buffer 105 converts the even and odd sampled bits DE and DO into a serial stream of data bits represented by analog differential signal VSP/VSN. Differential signal VSP/VSN is provided to inputs of tap driver 106. The differential output nodes of receiver 101 are coupled to input nodes of CDR circuit 103, the input nodes of DFE 102, and the differential output nodes of tap driver 106. Tap driver circuit 106 adjusts VOP/VON based on the serial stream of data bits represented by VSP/VSN. Tap driver circuit 106 receives bias current from current source 107. The bias current of current source 107 is programmable to provide different tap weights for tap driver 106.